Devesh Kumar

Full-stack web app for LPG gas meter management. Residents log in via email OTP, upload monthly meter photos, and track submission status. Admins review photos, enter readings, and mark them complete.

• JWT + email OTP auth via Azure Communication Services
• Meter photos stored in Azure Blob Storage; secrets managed via Azure Key Vault with Managed Identity
• CI/CD pipeline with GitHub Actions deploying to Azure App Service

Native Android app for day-wise inventory tracking across multiple companies and products. Fully offline with local SQLite storage and Excel export.

• Track stock in/out per day, view cumulative totals as of any date
• Export data to Excel (.xlsx) — one sheet per company — using Apache POI
• MVVM architecture with Room, Kotlin Coroutines, StateFlow, and Jetpack Compose Material 3

Scaled and optimised Liquid State Machine (LSM) architectures — spiking neural networks with Leaky Integrate-and-Fire neurons — for speech classification. Derived a mathematical model to predict optimal reservoir size, achieving 98% accuracy on TI-10 with only 1,250 trainable parameters vs. 18,500 for a comparable CNN.

• Preprocessed audio via Lyon Passive Ear Model + Ben's Spiking Algorithm (BSA) into spike trains across 77 channels
• Derived scaling formula: accuracy ≈ 100(1 − e^(−ReservoirSize/τ)) through curve fitting and linear interpolation
• Benchmarked across TI-10 (98%), TI-36 (73%), and Google Keyword (40%) datasets with 5-fold cross-validation

Comprehensive literature review of MTCNN architecture for facial recognition. Proposed computational improvements to enable deployment on multiple FPGAs simultaneously.

Applied backpropagation on a spiking neural network (SNN) trained on the MNIST dataset. Explored neuromorphic computing paradigms for efficient brain-inspired computation.

Implemented the DPLL algorithm in Python to solve NP-Complete boolean satisfiability problems. Applied unit clause propagation and pure literal elimination to significantly speed up solving.

Coded a 32-bit Brent Kung adder and 16-bit Dadda multiplier in VHDL with full test-bench verification. Created the schematic and performed component layout in Cadence Virtuoso.

Designed a 2-stage fully differential OTA with telescopic cascode in Cadence Virtuoso using 180nm SCL technology. Achieved 87dB DC gain and 70° phase margin post parasitic extraction.

Designed and fabricated a circuit for frequency sweep analysis of a blackbox to generate its bode plot. Configured a Krypton board to auto-generate sinusoidal signals from 20Hz to 20KHz.

Designed a power amplifier using AFIC901N on Keysight ADS achieving 20dB gain at 520MHz. Developed the PCB layout, fabricated on FR4 substrate, and verified with a Network Analyser.

Built a facial recognition system in Matlab using Fisher Discriminant Analysis and PCA on the cropped Yale dataset. Achieved 88% accuracy while handling lighting and facial variation.

Applied an RNN to predict phrasal categories and build parsed tree structures. Converted Penn Treebank to binary form via Chomsky Normal Form, collapsed unary rules, and used pre-trained word embeddings.

Designed a 16-bit RISC multicycle processor in VHDL with 14 instructions across three machine code formats. Demonstrated on FPGA with pipelining to reduce CPI.

Developed a system to wirelessly exchange encrypted messages between two Krypton boards. Configured a full keypad interface supporting A–Z, backspace, space, enter, and delete.

Programmed a CPLD to measure user reaction time between an LED trigger and button press, displaying scores on LCD in real time across five rounds. Cheat-proofed by disqualifying premature presses.